Computer processors and other devices (often operating under the control of a processor) frequently need to store or retrieve information in a computer memory. Memories usually permit access to any portion of the information they contain within an essentially constant amount of time. This property is indicated by the words “random access” in the name commonly applied to a type of computer memory, “random access memory” (“RAM”). Other types of memory also permit random access, though their names may indicate other important properties of the memory. For example, read-only memory (“ROM”), including electrically-erasable, programmable read-only memory (“EEPROM” or “Flash”) can also be accessed randomly. Random access storage contrasts with sequential access storage media, where access to one portion of the stored information may take significantly longer than access to another portion. For example, if information is stored on a magnetic tape, then retrieving information at the end of the tape may take much longer than retrieving information at the beginning.
Random access capability is often critical to adequate performance of applications on a general- or special-purpose computer. However, in some circumstances, memory access patterns may be perfectly predictable, or may be sufficiently regular that even a significant time penalty to begin accessing data can be tolerated by amortizing that penalty over a large number of operations. Also, in some applications, it may be known that the processor will never need to access only a single byte within a block of memory, but will only need to move the entire block from one place to another. In these and other similar situations, memory need not provide random access capabilities.
Whether computer memory is accessed randomly or sequentially, and as individual bytes or as larger blocks, its storage and retrieval functions are typically performed by electronic integrated circuits. The circuits are often packaged in a form known as a dual in-line memory module, or “DIMM.” This term will be used herein, but it should be recognized that the discussion applies equally to any memory device having the characteristics described, and not only to memories in the specific DIMM package.
DIMMs require electrical power to perform their storage and retrieval functions. The amount of power consumed during operation is generally proportional to factors such as the amount of storage provided and the speed of operation. For example, one 2 GB DIMM available on the market requires a current of 1.71 A at 1.8V (3.08 W) when storing or retrieving data. When not operating, but capable of responding immediately to a read or write command, the memory consumes 2.26 W. Other memory modules may consume different amounts of power.
Standard dynamic RAM (“DRAM”) devices available today (including synchronous DRAM, “SDRAM;” double data rate, “DDR” or “DDR1;” and double data rate version 2, “DDR2” devices) generally have a low power mode defined by the JEDEC Solid State Technology Association (formerly Joint Electron Device Engineering Council). This mode is called “self-refresh,” and is typically used by portable devices such as laptops when they are put into a “sleep” state for the sake of battery conservation. In self-refresh mode, the aforementioned 2 GB DIMM requires just 180 ma (324 mW), a power savings of almost 90%. Other memory modules may achieve greater or lesser power savings in self-refresh mode. A dynamic memory in self-refresh mode is different from a non-volatile memory such as EEPROM or Flash that can retain its contents even when power is completely removed. A DRAM in self-refresh mode continues to consume a small amount of power, and will lose its contents if power is interrupted.
Of course, the power savings offered by self-refresh mode come at a price. New information cannot be written to, and existing data cannot be retrieved from, a DIMM in self-refresh mode. If these functions of the memory are required, the “sleeping” memory must be “awoken:” it must go through a power-up procedure that may take many clock cycles, or that may restrict the memory to a lower-speed operational mode in lieu of those clock cycles. The time-consuming power-up procedure is necessary to permit the memory to synchronize its internal operations with an external clock by means of a delay-locked loop (“DLL”). In some systems, the synchronization may take significantly longer than the normal memory access time of only a few clock cycles, possibly exceeding the access time by a factor of 10 or more. Alternatively, some memories can be powered up and ready for operation within a few cycles (without performing synchronization), but in that event, access cycles may be limited to only a fraction of the full speed possible if the synchronization is performed.
In either case, switching DIMMs into and out of self-refresh mode to save power is not a promising strategy when the system's memory access patterns are not predictable, because the power-up time or performance penalties may be incurred whenever a DIMM containing required information is in low-power mode.
Although these discussions of DIMM power management operations have referred specifically to DIMMs that conform to the JEDEC DDR1 and DDR2 standards, it is expected that future versions of these standards (e.g. DDR3, DDR4, and so forth) will maintain similar power management capabilities and time or performance penalties for using them. Thus, the subsequent discussions will remain applicable to future DIMMs that implement descendants of DDR1 and DDR2. Also, other (non-JEDEC) memory modules may offer a “sleep” mode wherein the memory retains its contents, but cannot perform any of its other functions until a “wake” procedure is performed. The sleep mode will typically be associated with reduced power consumption, and the wake procedure will often impose a time or performance penalty. The subsequent discussions are relevant to this sort of memory module as well.